Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place!E‑Space is bridging Earth and space to enable hyper‑scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly‑advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.We're intentional, we're unapologetically curious and we're 100% committed to innovate space‑based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.WHAT YOU WILL BE DOING:Lead physical design implementation from floorplanning through GDSII sign‑off for complex SoC blocks and full‑chip designsPerform floorplanning, power planning, placement, clock tree synthesis (CTS), and routingDrive physical design closure meeting PPA (Power, Performance, Area) targets across all design cornersCollaborate with the STA team to analyze and resolve timing violations through ECO‑driven optimizationConduct and resolve physical verification (DRC, LVS, ERC) issues in partnership with the signoff teamDevelop and maintain physical design scripts, flows, and automation in Tcl/PythonWork with foundry process design kits (PDKs) and ensure design rule compliance on advanced nodesSupport integration of hard macros, memory compilers, and analog IP into top‑level designsAnalyze and optimize signal integrity, including crosstalk and noise effectsContribute to physical design methodology development and mentor junior engineersWHAT YOU BRING TO THIS ROLE:Minimum 8+ years of experience in physical design of complex digital ASICs or SoCsDeep expertise in Cadence Innovus, with broad familiarity with other P&R tools such as Synopsys ICC2Strong experience in floorplanning, power planning, placement, CTS, and routing for multi‑million gate designsDeep knowledge of timing‑driven physical design and working with STA engineers for timing closureExperience with physical verification tools (Mentor Calibre, Synopsys ICV) and DRC/LVS debugProficiency in scripting (Tcl, Python) for flow development and automationSolid understanding of low‑power design techniques (clock gating, power domains, UPF/CPF)Experience with advanced process nodes and associated PDK constraintsStrong problem‑solving skills and attention to detail in a deadline‑driven environmentBONUS POINTS:Experience with 7nm or sub‑7nm process nodesExposure to custom digital or mixed‑signal IC physical designFamiliarity with signal integrity analysis tools and methodologyExperience with hierarchical physical design flows for very large SoCsBackground in satellite, 5G, or IoT chip designThe target base pay for this position is $120,000–$220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job‑related knowledge, skills, and experience.This is a full‑time, exempt position, based out of our Saratoga office.We are redefining how satellites are designed, manufactured and used. If you have experience in LEO satellite component development, design and in‑orbit activities, we will be immediately wow‑ed.E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.#J-18808-Ljbffr