Intel seeks a Collateral - Design and DFM Lead Engineer to enhance methodologies improving performance and yield across advanced logic technologies. The role involves leading cross-functional teams to develop DFM rules, refine yield tools, and ensure design processes minimize yield issues.Successful applicants will have a Master's or Ph.D. in a relevant field with over 10 years of experience in semiconductor foundries. Compensation ranges from $190,650 to $269,150 USD annually, depending on experience.#J-18808-Ljbffr