A strong background in ASIC design
Proficiency in SystemVerilog
Experience with high-performance and power-efficient designs is highly desirable.
Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures
Master's degree in computer science or equivalent
3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience