790 Fusion Alliance jobs in Austin,TX

Ramos Agencies - San Marcos, TX

Arrow Electronics

Sunset Valley, TX 78745

Proficient in Verilog/System Verilog coding constructs.
Good in understanding RTL Design and Digital concepts
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
Strong experience with EDA tools: Fusion Compiler, CDC
Experience with IPXACT.
Experience with ARM Fabric IPs.
Experience with high speed PCIe designs and protocols.
Experience with Industry standard interface protocols such as AXI, APB, etc.
Understanding of Computer Architecture fundamentals.
AMBA AXI bus along-with ARM or C based processor
At-least 5+ years of experience in Verilog Design
Proficiency with UPF (Low power intent)
Proficiency in clock crossing techniques.
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Ability to write scripts using Python, Tcl, Perl etc.
Experience with EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
Scripting: Pearl, Python, TCL

Adecco

Austin, TX 78745

Minimum of 2 years of relevant experience, an AS degree in Electronics Technology (or equivalent military technical training), or a BSEET degree with hands-on experience of at least 2 years
Proficiency with hand tools, power tools, troubleshooting systems, and software applications such as MS Office, Oracle Manufacturing, and PDM
Capable of lifting up to 35 pounds
Working flexible hours, including overtime as needed

Arrow Electronics

Sunset Valley, TX 78745

Proficient in Verilog/System Verilog coding constructs.
Good in understanding RTL Design and Digital concepts
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
Strong experience with EDA tools: Fusion Compiler, CDC
Experience with IPXACT.
Experience with ARM Fabric IPs.
Experience with high speed PCIe designs and protocols.
Experience with Industry standard interface protocols such as AXI, APB, etc.
Understanding of Computer Architecture fundamentals.
AMBA AXI bus along-with ARM or C based processor
At-least 5+ years of experience in Verilog Design
Proficiency with UPF (Low power intent)
Proficiency in clock crossing techniques.
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Ability to write scripts using Python, Tcl, Perl etc.
Experience with EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
Scripting: Pearl, Python, TCL