A strong background in ASIC design
Proficiency in SystemVerilog
Experience with high-performance and power-efficient designs is highly desirable.
Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures
Master's degree or Ph.D. degree in Electrical Engineering or related field
Experience with formal verification techniques including abstraction and end-to-end checking
Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
Experience with industry standard tools and scripting languages (Python or Perl) for automation
Experience with ARM and various DSP ISAs