Bachelors degree with 8+ years, Masters degree with 6+ years, or PhD with 3+ years of relevant industry experience in a related field.
Deep expertise in digital communication systems, including high-speed and wireline communication architectures.
Deep expertise in digital signal processing (DSP) theory and practical implementation.
Strong background in physical layer (PHY) architecture and PHY layer development.
Proven experience in communication algorithm development, including designing and developing new algorithms rather than only implementing existing designs.
Strong programming experience in C
Experience using MATLAB to develop communication system models and perform algorithm development and analysis.
Experience defining communication system architecture and developing DSP algorithms for ASIC-based products.
Experience creating bit-accurate and fixed-point models for communication and DSP algorithms.
Experience developing simulation environments to evaluate system performance and validate architectural decisions.
Experience generating verification vectors and collaborating with ASIC implementation teams.
Experience supporting ASIC implementation efforts and working closely with ASIC design and verification teams.
Familiarity with ASIC architecture and development flows, including RTL correlation and validation.
Hands-on lab validation experience for communication systems or ASIC-based products.
Expertise in DSP algorithms such as equalization, timing recovery, channel estimation, synchronization, signal detection, and performance modeling.
Experience with fixed-point modeling, golden model development, verification vector generation, and ASIC implementation support.
Experience with Ethernet, twisted-pair communication systems, wireline communication architectures, high-speed data communications, and PHY layer development.
Experience working on ASIC-based communication products in a cross-functional environment with ASIC, verification, and hardware teams.
Experience defining verification strategies and detailed test plans for complex communication systems.
Background in golden model development for DSP and communication algorithms to support verification flows.
Experience with RTL correlation and validation for communication and DSP blocks.
Exposure to Ethernet and high-speed wireline standards and their impact on PHY and DSP design.
