The ideal candidate will have a strong background in ASIC design, proficiency in SystemVerilog, and excellent analytical and problem-solving skills.
Experience with high-performance and power-efficient designs is highly desirable.
Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures
Master's degree in Electrical or Communications Engineering or a related field
Experience with formal verification techniques including abstraction and end-to-end checking
Experience with ARM and various DSP ISAs
Experience with current and upcoming RF standards in cellular (4G/5G NR), WiMAX, 802.11ad, microwave backhaul, or related broadband wireless standards
Experience with industry standard tools and scripting languages (Python or Perl) for automation