Proven experience in DRAM architecture and circuit design (HBM, DDR, LPDDR, GDDR, or equivalent)
Strong understanding of DRAM array architecture, row/column paths, sensing, datapath, refresh, and reliability mechanisms
Hands‑on experience with SPICE‑based circuit simulation tools (HSPICE, Spectre, FineSim, PrimeSim, or equivalent)
Ability to evaluate performance, power, area, thermal, and reliability trade‑offs
Experience driving architecture decisions and cross‑functional technical execution
