Proficient in DSP algorithms and its implementation onto the FPGA using MATLAB and SimuLink.
Strong design skills in VHDL & Verilog.
Experience in FPGA physical constraints and achieving timing closure.
Experience in developing low-level FPGA requirements and developing verification procedures.
Background in RF design is a plus.
Experience with board or system level debug using test equipment such as oscilloscopes, logic and spectrum analyzers, RF signal generator, etc.
Generation of complex test benches in Modelsim or Questasim to support formal Verification.
Familiarity with the VxWorks RTOS, its architecture and development tools is a plus.
Expertise in high-speed FPGA implementation such as AXI, DMA, PCIe, HSSI, DDR3, Ethernet, etc.
