Experience: 6+ Years
At-least **6+ years of experience** in **System Verilog HVL and C++/C**
At-least 6+ year of experience in **UVM.**
Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
Proficient in **SVTB/UVM, C++ testbench**
**Proficient in debug** and assertions coding
At-least 6**\+ years of experience** in **System Verilog HVL and C++/C**
**Make/Perl/Python / any script**
**Any protocol experiace is fine**
Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.