Professional Level Design Engineer

Newark,CA

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2127 Professional Level Design Engineer jobs in Newark,CA

Featured Opportunity

Automotive Tool Sales/Route Manager - Full Training

Mac Tools - San Mateo, CA

Mac Tools - San Mateo, CA

Automotive Tool Sales/Route Manager - Full Training

Flexible Schedule

New, Posted 8 hours ago

Senior Software Engineer for Athlete Performance Research

Another source

Palo Alto, CA 94306

New, Posted 1 day ago

Hydrogeologist - Mid- or Senior Level

Montgomery & Associates

Oakland, CA 94605

New, Posted 14 hours ago

Border Patrol Agent (BPA) Entry Level - New Hire Sign-On and Retention Incentives

U.S. Customs and Border Protection

Dublin, CA 94568

$51,632-$92,219/yr

Urgently HiringBilingual Preferred

New, Posted 1 day ago

Hydrogeologist - Mid- or Senior Level

Montgomery & Associates

Oakland, CA 94606

New, Posted 14 hours ago

Warehouse Manager

Gexpro Services

Livermore, CA 94551

Border Patrol Agent – Entry Level (Up to $60K Incentives)

United States Customs and Border Protection

Fremont, CA 94536

$49,739-$89,518/yr

Bilingual Preferred

New, Posted 14 hours ago

Customs and Border Protection Officer (CBPO) - Entry Level New Hire Sign-On and Retention Incentives

US Customs and Border Protection

Union City, CA 94587

$40,332-$109,952/yr

Bilingual Preferred

Principal Sales Engineer - Warehouse Robotics Systems

SKILD AI

San Mateo, CA 94403

New, Posted 16 hours ago

High Speed SerDes DSP RTL Designer

Broadcom

San Jose, CA 95112

~ 29 min OnsiteHealth InsurancePaid Time OffRetirement Benefit

MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design.
Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration.
Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint.
Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
Experience in synthesis, CDC, static timing analysis.
Exposure to SDF annotated simulations with good understanding of parasitic delays.
Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
Strong analytical thinking and problem-solving skills with excellent attention to details.
Must be organized, self-motivated and able to work effectively across internal and end customers teams.
Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.

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New, Posted 8 hours ago

Software Engineer for Athlete Performance Research

Another source

Palo Alto, CA 94306

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