928 Python Backend Engineer jobs in Palo Alto,CA

The salary will vary depending on your job-related skills, experience and location.

Pay increment and frequency of pay will be in accordance with employment classification and applicable laws.

Healthcare benefits including medical & prescription drug coverage, dental, vision, and mental health & well being

Financial programs such as 401(k), cash balance pension plan, the IBM Employee Stock Purchase Plan, financial counseling, life insurance, short & long- term disability coverage, and opportunities for performance based salary incentive programs

Generous paid time off including 12 holidays, minimum 56 hours sick time, 120 hours vacation, 12 weeks parental bonding leave in accordance with IBM Policy, and other Paid Care Leave programs. IBM also offers paid family leave benefits to eligible employees where required by applicable law

Training and educational resources on our personalized, AI-driven learning platform where IBMers can grow skills and obtain industry-recognized certifications to achieve their career goals

Diverse and inclusive employee resource groups, giving & volunteer opportunities, and discounts on retail products, services & experiences

You'll be on-call for all of it.

5+ years industry experience designing, building, scaling and supporting backend systems in production

Proficiency in a major programming language, e.g. Java, Go, C / C++, Python, etc

Experience in driving operational excellence for large production services

Proven track record of delivering large-scale, highly available, high quality systems

Hands-on technical expertise in large scale systems engineering or distributed systems

On-call experience handling critical systems

This role may be eligible for incentive pay and/or equity.

$217,000—$299,999 USD

Flexible time off

Wellness resources

Company-sponsored team events.

Deep technical proficiency in architecting and shipping large-scale enterprise software, with specific experience in high-availability systems, cloud-native technologies, or storage protocols.

Proven experience managing and growing software engineering teams

Mastery of delivery management and lean engineering processes

$209,300.00 - $313,900.00

Competitive annual discretionary bonus program

Opportunity for annual RSU grants

Our highly competitive benefits package is designed to support your success at work, at home, and at play.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Industry experience of Static Timing Analysis (STA) on cutting edge technology nodes

Programming/Scripting skills (Python and Tcl in particular)

Coding with a focus on quality and reusability. Leverage static checking, Test Driven Development, CI/CD, etc to achieve high quality software

Experienced in generating/optimizing/automating timing ECO closure

Detailed understanding of STA concepts (e.g.: LVF/CCS/SSI/NBTI) and how they impact margins/derates

Debugging/Support with project deadlines in mind

Synthesis/PnR experience with a focus on PPA optimization.

Web/Database/Dashboards/Visualization experience a plus.

Experience applying AI techniques to EDA workflows, including log analysis, root-cause investigation, metrics mining, knowledge retrieval, and automated generation of scripts, documentation, and test collateral.

Competitive financial compensation, including various compensation plans

Solid benefits package

Medical, Dental, Vision Insurance

401k, With Matching Contributions

Short-Term/Long-Term Disability Insurance

Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Full time

At-least **6+ years of experience** in **System Verilog HVL and C++/C**

At-least 6+ year of experience in **UVM.**

Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.

Proficient in **SVTB/UVM, C++ testbench**

**Proficient in debug** and assertions coding

**Make/Perl/Python / any script**

**Any protocol experiace is fine**

Understand DSP is a plus

Subversion for Repository and Bugzilla is also a Plus

$142,000-$242,000

Additional compensation may include benefits, bonuses, and equity.

Medical, dental and vision plans

Paid family leave

A robust paid time-off program and paid holidays

Full-time position

Bachelor's degree or equivalent practical experience

5+ years in design, product, test, systems, or applications engineering with DRAM, HBM, SSD, or compute systems

Experience with server architecture, hardware design, or system troubleshooting

Knowledge of memory interfaces and memory usage in server environments

Apply Artificial Intelligence tools

Experience with datacenter server management and logging tools (e.g., BMC, EMC, EDAC)

Background in quality and reliability engineering

Willingness to travel and support customer engagements

Your Amazon package will include sign-on payments and restricted stock units (RSUs).

USA, CA, San Diego - 185,200.00 - 250,000.00 USD annually

USA, CA, Sunnyvale - 213,000.00 - 287,500.00 USD annually

USA, WA, Redmond - 185,200.00 - 250,000.00 USD annually

Health insurance (medical, dental, vision, prescription, Basic Life & AD&D; insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)

401(k) matching

Paid time off

Parental leave

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent work experience

7+ years of experience in silicon test, security engineering, or test software development.

Experience with device security and secure provisioning during test, including OTP/eFuse programming.

Working knowledge of the fundamentals of encryption, cryptographic keys, and secure communication channels.

Strong software engineering skills, including proficiency in a language such as Python and/or C/C++, and experience building reusable, well-architected code.

Experience developing test or automation software on Advantest 93K and/or Teradyne UltraFLEX platforms.

International travel required during release-to-production phases.

Master's degree in Electrical/Computer Engineering or Computer Science.

Expertise in standard silicon security concerns for modem and SoC devices, such as secure boot, secure key and identity provisioning, fuse-based lifecycle management, and debug-port lockdown.

Experience implementing cryptographic provisioning flows involving keys, certificates, and device identities in a manufacturing or test environment.

Experience working with anti-tamper and physical security blocks in silicon, such as tamper detection, sensors, and secure-element hardening.

In-depth understanding of OTP/eFuse programming challenges, including margin, read-back verification, repeatability, and managing irreversible operations at high volume.

Strong software development background, with experience building reusable ATE libraries and tooling (pattern search, sub-flow generation, automated test-program generation).

Experience with digital test of complex SoCs, including developing, debugging, and analyzing coverage for scan/ATPG, MBIST, boundary scan (JTAG), and functional tests.

Experience developing and debugging test programs on ATE platforms such as Advantest 93K and Teradyne UltraFLEX.

Experience with high-speed SERDES test and characterization, including equalization test and tuning (CTLE/DFE/FFE), jitter decomposition, and eye/BER analysis.

Experience developing high-volume manufacturing test solutions and driving the full test release process across the New Product Introduction (NPI) lifecycle, from silicon bring-up, characterization, and qualification through production hand-off and ramp.

Familiarity with I/O protocols such as I3C, SPI, and GPIO.

Experience testing complex modem and SoC devices in advanced process nodes.