6–8 years of experience in ASIC/SoC STA, synthesis (including low power), timing constraint development, Low power checks and functional ECO implementation.
Deep knowledge of Static Timing Analysis (STA), and timing constraints.
Experience with Multi Mode Multi Corner (MMMC) timing closure, OCV/AOCV/POCV, and advanced technology nodes.
Experience with timing closure sign off requirements.
Experience in Synthesis, Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist).
Understanding of SOC clocking and reset methodology and implementation.
Scripting skills in TCL and Perl.
Exposure to Low implementation techniques and design checks (multi-voltage designs, UPF).
Hands‑on experience with:
Synopsys Prime Time
Synopsys Design Compiler / Cadence Genus
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.