Verilog and System-Verilog languages
RTL integration, partitioning, transformation, and analysis.
Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock domain crossing checks.
Package, qualify and deliver FE design collateral.
Develop innovative methods to improve front-end design integration process.
Collaborate effectively with Architecture, Design, DV, SOC, DFT, and IMPL teams spanning multiple sites.
Version control systems
RTL synthesis using physically aware tools
Formal Verification using industry standard tools for RTL-netlist and netlist-netlist checks
ECO methods for functional and timing fixes
Managing design goals in power, performance and area
Experience with UNIX, Perl, TCL or shell scripting
Ability to analyze architectural and micro architectural details to drive design partitioning.
Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA.
Excellent interpersonal and analytical skills as well as ability to work independently
Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented
