1271 Associate Software Engineer jobs in San Jose,CA

The annual base salary range is: $217,000—$326,000 USD

This role may be eligible for incentive pay and/or equity.

Flexible time off

Wellness resources

Company-sponsored team events

Deep architectural expertise in high-density x86 enterprise server systems, rack-scale power delivery topologies (power-tree modeling, transient analysis), dynamic thermal management, high-performance storage protocols (NVMe-oF, CXL), and multi-node rack architectures.

Extensive experience executing complex system bring-ups, high-speed signal integrity validation (PCIe Gen 5/6, high-frequency buses), and deep-dive hardware failure analysis using advanced lab instruments and telemetry architectures (BMC, Redfish, IPMI, PCIe analyzers, SMART logs).

Proven success building scalable, programmatic validation pipelines (Python/Shell) and rigorous system stress testing methodologies to qualify enterprise-grade L10/L11 infrastructure.

Demonstrated expertise in setting up, validating, and debugging rack-level interconnectivity spanning servers, high-speed switches, active optics, and fabric topologies.

Familiarity with leaf-spine networks, RoCE, RDMA, InfiniBand, and BGP is highly desirable.

This role requires an in-office presence at our **Santa Clara, CA** headquarters

Familiarity with leaf-spine networks, RoCE, RDMA, InfiniBand, and BGP is highly desirable.

Sign-on payments

Restricted stock units (RSUs)

USA, CA, Cupertino - 176,600.00 - 247,300.00 USD annually

USA, TX, Austin - 153,600.00 - 215,000.00 USD annually

Health insurance (medical, dental, vision, prescription, Basic Life & AD&D; insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)

401(k) matching

Paid time off

Parental leave

Experience scripting or coding

BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS

Expertise in timing analysis fundamentals

1+ years doing Static Timing Analysis

1+ years with timing constraint development

Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others)

Understanding of ASIC Physical Design from RTL-to-GDSII

Understanding of other sign-off activities (ir/em, physical verification, DFT)

1+ years of scripting experience with Tcl, Perl or Python

Expertise developing flows using STA tools (examples: PrimeTime, Tempus or others)

Expertise in ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker or others)

Experience in advanced nodes - 16nm or below

Expertise in parasitic extraction tools (examples: STAR-RC, Quantus or others)

Expertise on circuit level analysis using tools like SPICE / SPECTRE

Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die etc.