Master's degree in Electrical/Computer Engineering or Computer Science.
Demonstrated ability to lead cross-functional technical efforts and mentor other engineers.
Expertise in standard silicon security concerns for modem and SoC devices, such as secure boot, secure key and identity provisioning, fuse-based lifecycle management, and debug-port lockdown.
Experience implementing cryptographic provisioning flows involving keys, certificates, and device identities in a manufacturing or test environment.
Experience working with anti-tamper and physical security blocks in silicon, such as tamper detection, sensors, and secure-element hardening.
In-depth understanding of OTP/eFuse programming challenges, including margin, read-back verification, repeatability, and managing irreversible operations at high volume.
Strong software development background, with experience building reusable ATE libraries and tooling (pattern search, sub-flow generation, automated test-program generation).
Experience with digital test of complex SoCs, including developing, debugging, and analyzing coverage for scan/ATPG, MBIST, boundary scan (JTAG), and functional tests.
Experience developing and debugging test programs on ATE platforms such as Advantest 93K and Teradyne UltraFLEX.
Experience with high-speed SERDES test and characterization, including equalization test and tuning (CTLE/DFE/FFE), jitter decomposition, and eye/BER analysis.
Experience developing high-volume manufacturing test solutions and driving the full test release process across the New Product Introduction (NPI) lifecycle, from silicon bring-up, characterization, and qualification through production hand-off and ramp.
Familiarity with I/O protocols such as I3C, SPI, and GPIO.
Experience testing complex modem and SoC devices in advanced process nodes.