4485 Enterprise Architect jobs in San Jose,CA

The base pay range for this role is between $151,000 and $251,800.

Eligible for MBO bonus compensation

Eligible to participate in long term incentive plan

Medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more.

Relocation

6+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master's degree, or 2+ years of experience with a PhD

Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs

Demonstrated successful architectural through RTL design experience on high performance digital designs

Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

Knowledge of system caches and directory snoop filter protocols.

Familiarity with different on-chip network topologies: mesh, ring, crossbar.

Experience in leading and mentoring a team of engineers.

Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols

Knowledge of memory subsystem design including coherent cache design.

Applicants must be authorized to access such information or eligible for government authorization.

Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.

Proficient in AMBA, ACE, AXI, CHI protocols.

Knowledge of coherent interconnect, memory controller, and/or cache design.

Knowledge of memory subsystem, coherency, directory snoop filter protocols.

Familiarity with different on-chip network topologies: mesh, ring, crossbar.

Experience with a scripting language like Perl or Python.