1410 Software Qa Engineer jobs in San Jose,CA

**Santa Clara, CA pay range: MIN $110,660 - MIDPOINT $147,540 - MAX $184,430**

This role is eligible for Keysight Results Bonus Program

Medical, dental and vision

Health Savings Account

Health Care and Dependent Care Flexible Spending Accounts

Life, Accident, Disability insurance

Business Travel Accident and Business Travel Health

401(k) Plan

Flexible Time Off, Paid Holidays

Paid Family Leave

Discounts, Perks

Tuition Reimbursement

Adoption Assistance

ESPP (Employee Stock Purchase Plan)

Bachelor's degree in Manufacturing Engineering, Mechanical Engineering, Materials Science, Physics, or a related technical field

5+ years of hands-on manufacturing engineering experience in a precision manufacturing environment

Experience in **most** of the following technical areas is preferred: * Scientific glass processing equipment * Properties of optical-grade glass and glass coatings * Properties and behavior of metal alloys * Vacuum processing and partial pressure analysis * Chemical composition analysis * Mechanical component inspection and metrology * Gas laser theory (HeNe preferred) * Statistical Process Control (SPC) methods and analysis * Process automation

$160,000-$211,000 USD

Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package.

Anduril offers top-tier benefits for full-time employees

Minimum of 5 years of industry experience as a System Safety Engineer or equivalent engineering background

B.S. degree in Mechanical Engineering, Aerospace Engineering, Systems Engineering, or equivalent technical discipline

Experience with safety-critical hardware and software systems in the defense or aerospace industry

Familiarity with MIL-STD-882E and other relevant safety standards

Strong background in safety analysis techniques including FTA, FHA, SCFTA, and FMECA

Experience with requirements decomposition for Safety

Failure investigation/analysis experience with a proven track record of solving problems and preventing reoccurrence

Design Review experience (PDR, CDR, MRR)

Eligibility to obtain and maintain a U.S. security clearance

By submitting your application, you consent to Anduril Industries using a third-party service provider to conduct pre-employment risk, integrity, and due diligence screening and assessing potential risks as part of your application process.

M.S. degree in Mechanical Engineering, Aerospace Engineering, Systems Engineering, or equivalent technical discipline

Experience or familiarity with ARP-4754, ARP-4761, MIL-STD-516C, and JSSSEH

Experience with Relyence, Teamcenter, JIRA, JAMA, Cameo, and/or Ansys

Software safety case development experience

Experience with risk management, change control/change management reviews, and software/firmware HITL/SITL

AI/ML software safety experience

Competitive pay, stock bonuses

$220,920.00-311,890.00 USD

Health, retirement, and vacation

Shift 1 (United States of America)

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience in RTL design for ASIC/SoC development; OR Master's degree in relevant field with 8+ years of experience; OR PhD in relevant field with 6+ years of experience.

Advanced proficiency in RTL design using Verilog/SystemVerilog and hands-on experience in SoC system integration.

Expertise in standard bus protocols (AXI, AHB) and embedded processor architectures.

Proficiency in scripting languages (e.g., Python, TCL) for automation and design flow customization.

Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks.

Strong knowledge of high-speed and low-power design techniques.

Familiarity with industry-standard EDA tools such as HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).

Experience in SoC multicore CPU subsystem design and GPU cache development.