1919 Professional Level Process Engineer jobs in San Marcos,TX

Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement.

Medical, dental, and vision insurance

Three weeks of vacation for newly hired employees

Generous 401(k) plan that includes employer matching funds and separate employer retirement contribution, including a Lifetime Income Strategy option

Tuition reimbursement program

Student Loan Repayment Program

Life insurance and disability coverage

Optional coverages you can buy: pet insurance, home and auto insurance, additional life and accident insurance, critical illness insurance, group legal, ID theft protection

Birth, adoption, parental leave benefits

Ovia Health, fertility, and family planning

Adoption Assistance

Autism Benefit

Employee Assistance Plan, including up to 10 free counseling sessions

Healthy You Incentives, wellness rewards program

Doctor on Demand, virtual doctor visits

Bright Horizons, child and elder care services

Teladoc Medical Experts, second opinion program

Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays.

2nd Shift: 3P - 11:30P

Must be authorized to work in the U.S. without the company's immigration sponsorship now or in the future.

Typically requires HS diploma (or equivalent, e.g. G.E.D. in the US) or vocational/technical education in related discipline with a minimum of 1 year of relevant experience

1 or more years of experience within a Manufacturing environment

Experience reading and interpreting blueprints, diagrams, and engineering drawings to assemble equipment..

Experience with any of the following: hand tools, electrical tools, hand cutters, measuring equipment and light equipment.

Relevant manufacturing, assembly, and/or construction / facilities experience

Full-Time Salary Range: $132962 - $226035

Health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance.

An employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance.

Paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave.

9/80 work schedule

Full-Time

Active Secret Security clearance

Bachelors degree in an engineering discipline, and at least six years of experience in engineering development of complex electronic systems

Experience leading diverse multi-disciplinary teams in the solution of complex technical problems

Experience with hardware development projects in a defense environment including organizational design, planning, estimating, design management, and product verification

Experience using Design to Cost (DTC) methods; leading to technical solutions that meet affordability and producibility requirements

Earned Value Management System (EVMS) and cost account management (CAM) experience

Familiarity with development of EO/IR products for military applications (lasers, cameras, sensors, pointers)

Sign-on payments and restricted stock units (RSUs)

114,600.00 - 160,400.00 USD annually

Health insurance (medical, dental, vision, prescription, Basic Life & AD&D; insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)

401(k) matching

Paid time off

Parental leave

Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field, or equivalent experience

2+ years in verification

2+ years in UVM

Candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Preferably in communication systems

Master's or Ph.D degree in Electrical / Communications Engineering

3+ years in digital verification, preferably in communication systems

Familiarity with Matlab

Modem design verification experience

System C, C or Matlab model : development or DV integration experience

Comfortable using AI-assisted tools to accelerate verification workflows (testbench generation, debug, coverage analysis).

Familiarity with formal verification techniques

This role is ideal for a seasoned engineer

$129,500.00 - $194,300.00

Competitive annual discretionary bonus program

Opportunity for annual RSU grants

Our highly competitive benefits package

Excellent automation skills using TCL/Perl/Python

Be able to develop/work on automation scripts with the given spec to develop CPU STA signoff flow /methodology

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/Tempus

History of any framework /tool /utility development is preferred

Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

Hands-on experience with STA tools - Prime-time, Tempus

Have experience in driving timing convergence at Chip-level and Hard-Macro level

In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)

Basic knowledge of device physics