Experience scripting or coding
BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS
Expertise in timing analysis fundamentals
1+ years doing Static Timing Analysis
1+ years with timing constraint development
Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others)
Understanding of ASIC Physical Design from RTL-to-GDSII
Understanding of other sign-off activities (ir/em, physical verification, DFT)
1+ years of scripting experience with Tcl, Perl or Python
