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Design Intern

Santa Clara,CA

2447 Design Intern jobs in Santa Clara,CA

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Arrow Electronics - San Jose, CA

Physical Design Engineer II (IC)
~ 16 min Onsite
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User Experience Design Intern, BS/MS, Summer 2027

Google

Palo Alto, CA 94301

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Software Engineering - Intern, Graduate

Intel

Santa Clara, CA 95054

New, Posted 11 hours ago
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Customer Success JOB Training Program

Year Up United

San Jose, CA 95101

$525/wk
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Annapurna Labs (U.S.)

Cupertino, CA 95014

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Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

~ 16 min OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 6+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master's degree, or 2+ years of experience with a PhD
  • Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
  • Demonstrated successful architectural through RTL design experience on high performance digital designs
  • Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Knowledge of system caches and directory snoop filter protocols.
  • Familiarity with different on-chip network topologies: mesh, ring, crossbar.
  • Experience in leading and mentoring a team of engineers.
  • Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
  • Knowledge of memory subsystem design including coherent cache design.
  • Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
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New, Posted 14 hours ago
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Principal Tooling Design Engineer

Northrop Grumman

Sunnyvale, CA 94087

~ 14 min OnsiteEducation AssistanceHealth InsurancePaid Time Off

  • Bachelor's in a STEM discipline (Science, Technology, Engineering, or Math) with a minimum of 5 years of technical experience in design for manufacturing (DMF); master's degree in a STEM discipline with 3 years of experience.
  • Experience in 3D CAD modeling using standard commercial CAD software.
  • Experience in 2D drafting and drawing creation from 3D models.
  • Experience modifying existing 2D drawings and 3D CAD models.
  • U.S. citizenship required.
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New, Posted 20 hours ago
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Senior Laser Designer

Intel Corporation

Santa Clara, CA 95051

OnsiteHealth InsurancePaid Time OffRetirement Benefit

  • Master's degree in a relevant field such as Electrical Engineering, Physics, or a related discipline with 6+ years of relevant experience OR Ph.D. with 4+ years of industry expertise.
  • Extensive experience in designing and simulating DFB lasers including InP epi design.
  • Industrial experience developing DFB lases in high volume manufacturing, including taking designs through product qualification.
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Sr Principal TIA Designer

Nokia

Sunnyvale, CA 94089

~ 14 min Onsite

  • Lead the architecture, design, simulation, verification, and silicon bring-up of ultra-high-speed Transimpedance Amplifiers (TIAs) for coherent optical and PAM4 data center applications
  • Translate system and chip-level requirements into robust analog circuit architectures and detailed transistor-level designs
  • Design and optimize low-noise, high-linearity broadband analog circuits for optical receiver front ends
  • Develop and validate supporting analog functions, including AGC loops, CTLEs, voltage regulators, bandgaps, and data converter interfaces
  • Drive package and system-level integration, ensuring optimal signal integrity and performance
  • Perform silicon characterization, debug, and correlation of measurement results against simulation models
  • Collaborate closely with layout, system, DSP, packaging, and product engineering teams throughout the development cycle
  • Lead technical reviews, contribute to design methodology improvements, and ensure successful first-pass silicon execution
  • Mentor and guide junior analog designers, fostering technical excellence within the team
  • Create and maintain high-quality technical documentation, design reports, and specifications
  • Extensive experience designing high-speed TIAs for coherent optical communication systems and/or PAM4 data center transceivers
  • Strong expertise in analog and mixed-signal IC design using SiGe BiCMOS and CMOS technologies
  • Deep understanding of transistor-level circuit design, device physics, noise analysis, and feedback/control loop stability
  • Proven experience in one or more of the following areas: Optical receiver front-end design, AGC loop implementation, CTLE design, High-precision analog circuits (bandgaps, regulators, ADC/DAC interfaces), Package and system-level integration
  • Proficiency with industry-standard EDA tools, custom analog layout techniques, and electromagnetic (EM) simulation tools
  • Demonstrated success delivering silicon from concept through production
  • Hands-on experience with lab measurement, debugging, and performance validation of high-speed ICs
  • Strong leadership, problem-solving, communication, and collaboration skills
  • Ability to work effectively in a fast-paced, multidisciplinary global engineering environment
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Data Center Lab Designer / Architect

Advanced Micro Devices

San Jose, CA 95124

Hybrid~ 16 min

  • Data Center Lab Designer / Architect
  • Lead technical evaluation, lab design strategy, infrastructure standards, and construction oversight for high-density data center environments
  • Site readiness, infrastructure scalability, and deployment execution align with AMD's performance, efficiency, and 3-5 year product roadmap requirements
  • Set global lab design direction across business units and use cases
  • Strong design leadership and project execution skills
  • Devise strategies for complex, high-density compute environments
  • Align cross-functional teams to deliver against active project milestones
  • Establish global design standards across labs and business units
  • Strong analytical thinking, executive communication, and stakeholder alignment skills
  • Plan infrastructure evolution aligned to future product roadmaps
  • Identify risk early and drive mitigation through structured governance
  • Data Center Due Diligence & Strategic Assessment: Perform technical due diligence on new and existing facilities
  • Evaluate power availability, redundancy, cooling capacity, environmental risk, connectivity, and expansion potential
  • Review infrastructure drawings, layouts, and single-line diagrams
  • Assess design maturity (Concept through IFC) and contractor capability
  • Identify technical, schedule, and scalability risks with structured reporting
  • Validate infrastructure alignment with high-density and future roadmap requirements
  • Lab Design & Global Standards Leadership: Develop scalable, modular lab designs optimized for density, airflow, accessibility, and operational efficiency
  • Set direction and define global lab design standards across AMD BUs and use cases
  • Ensure compliance with industry standards and evolving best practices
  • Integrate energy-efficient and sustainable design principles into all deployments
  • Utilize advanced modeling and simulation tools for airflow and thermal validation where required
  • Infrastructure Strategy & Technology Integration: Define corporate standards for power distribution, cooling systems, IT networking space, and rack density
  • Assess and implement high-density and liquid cooling readiness
  • Support integration of renewable energy strategies and advanced cooling technologies
  • Lead implementation and governance of DCIM, monitoring, and automation platforms
  • Ensure modular and POD-based expansion strategies support long-term scalability
  • Construction Monitoring & Deployment Governance: Monitor construction progress, quality, and contractor performance
  • Evaluate supply chain readiness for critical long-lead infrastructure components
  • Track execution against schedule and budget constraints
  • Lead design reviews and ensure alignment between intent and build
  • Oversee commissioning and validate operational readiness prior to deployment
  • Stakeholder & Program Management: Lead cross-functional collaboration across IT, Facilities, Real Estate, Procurement, and Product SMEs
  • Manage multiple concurrent projects while maintaining delivery timelines
  • Liaise with vendors and contractors to ensure installation timelines and standards adherence
  • Provide executive-level reporting on risk, budget, and schedule health
  • Maintain detailed documentation of specifications, assessments, and progress tracking
  • Preferred Experience: Semiconductor or high-density data center design, construction, or operations
  • Proven experience in large-scale lab or data center architecture and build-outs
  • Strong background in infrastructure assessment and technical due diligence
  • Experience reviewing construction drawings and overseeing commissioning
  • Familiarity with high-density computing, cloud-scale environments, and high-performance networks
  • Experience with airflow modeling or thermal simulation tools
  • Knowledge of DCIM and infrastructure monitoring systems
  • Relevant data center certifications (DCCA, CDCDP, or similar) preferred
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