3931 Vice President Intel Gpu Ai Architecture jobs in Santa Clara,CA

Competitive pay, stock bonuses

$220,920.00-311,890.00 USD

Health, retirement, and vacation

Shift 1 (United States of America)

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience in RTL design for ASIC/SoC development; OR Master's degree in relevant field with 8+ years of experience; OR PhD in relevant field with 6+ years of experience.

Advanced proficiency in RTL design using Verilog/SystemVerilog and hands-on experience in SoC system integration.

Expertise in standard bus protocols (AXI, AHB) and embedded processor architectures.

Proficiency in scripting languages (e.g., Python, TCL) for automation and design flow customization.

Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks.

Strong knowledge of high-speed and low-power design techniques.

Familiarity with industry-standard EDA tools such as HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).

Experience in SoC multicore CPU subsystem design and GPU cache development.

$221,100.00 - $331,700.00

Competitive annual discretionary bonus program

Opportunity for annual RSU grants

Our highly competitive benefits package is designed to support your success at work, at home, and at play.

Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products.

Strong understanding of Ethernet, InfiniBand, RoCEv2, RDMA, and related transport protocols.

3+ years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems.

Strong knowledge of scale-out networking and scale-up interconnect architectures for AI and cloud infrastructure.

In-depth knowledge of Ethernet, high-speed SerDes, PCIe/CXL-class interfaces, and board/system-level connectivity tradeoffs.

Strong understanding of telemetry, observability, RAS, reliability, error handling, and failure-mode analysis in large-scale systems.

Strong understanding of security, isolation, virtualization, and multi-tenant deployment requirements in datacenter environments.

Strong understanding of DMA engines, memory hierarchy, I/O virtualization, and accelerator data-movement architectures.

Good understanding of PCIe, CXL, and UCIe protocols and their use in accelerator, server, and rack-scale architectures.

Familiarity with Ethernet switch management and control-plane ecosystems such as SONiC, SAI, OpenBMC, Linux networking, and related platform software.

Good understanding of high-speed SerDes and Ethernet PHY design considerations, including signal integrity, reach, power, latency, and platform tradeoffs.