Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Experience in handling complex data path oriented Multi-million gate synthesis.
Working Knowledge on Physical synthesis using tools like DC, Genus, Fusion Compiler
Experience in developing constraints for multi-clock domains hierarchical/flat timing analysis
Good working knowledge in multi-power domain synthesis and structural power checks using CLP.
Hands-on experience in Formal verification along with strong debugging skills for resolving issues/aborts.
Good working knowledge in Pre-layout STA and analyzing timing reports and generating timing ECOs
Good knowledge on analyzing trade-offs and recipes for timing/area/power/congestion.
Exposure in TCL scripting for usage in Synthesis/STA
