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FPGA Design - Lead Research Engineer "CLEARANCE REQUIRED"

GE Vernova

Schenectady, NY 12309

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Lead Research Engineer

GE Vernova

Niskayuna, NY 12309

OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

Ph.D. in Computer Science, Electrical Engineering, or related disciplines OR Master's degree in Computer Science, Electrical Engineering, or related disciplines with a minimum of 2 years of industry experience OR Bachelor's degree in Computer Science, Electrical Engineering, or related disciplines with a minimum of 5 years of industry experience.
2-5 years of strong FPGA and SoC design experience using Verilog, SystemVerilog and VHDL
2-5 years of hands-on experience with Xilinx and/or Intel (Altera) FPGA devices, tools, and ecosystems (e.g., ModelSim, Intel Quartus, Xilinx Vivado)
2-5 years of solid understanding of digital logic design, including FSMs, pipelining, and resource optimization.
2-5 years of experience with RTL simulation, synthesis, place-and-route, and timing closure
2-5 years of knowledge of clock domain crossing (CDC) techniques and metastability mitigation
2-5 years of familiarity with high-speed and standard interfaces (UART, SPI, I²C, Ethernet, PCIe, DDR)
2-5 years of experience developing testbenches and performing functional verification.
2-5 years of proficiency with on-chip debugging tools (e.g., ILA, SignalTap)
2-5 years of ability to read and interpret schematics, timing diagrams, and hardware datasheets
2-5 years of experience using version control systems (Git preferred)
2-5 years of experience with high-level synthesis (HLS) tools and algorithm-to-hardware workflows, including Vitis HLS and integration with MathWorks MATLAB/Simulink for model-based design and verification.
Legal authorization to work in the US is required.
We will not sponsor individuals at the Bachelor's level for employment visas, now or in the future, for this job opening.
Must be willing to work out of an office located in Niskayuna, NY
This role requires access to U.S. export-controlled information. If applicable, final offers will be contingent on ability to obtain authorization for access to U.S. export-controlled information from the U.S. Government.
2-5 years of hands-on experience with Xilinx and/or Intel (Altera) FPGA devices, tools, and ecosystems\n(e.g., ModelSim, Intel Quartus, Xilinx Vivado)