2192 Dsp Engineer jobs in San Jose,CA

#Sr. Engineer, CPU Software Test Engineer (Server)

Qualcomm

Santa Clara, CA 95053

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience.
OR Master’s degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience.
OR PhD in Engineering, Information Systems, Computer Science, or related field.
• 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Hire Standard Staffing

San Jose, CA

Must be a U.S. or Canadian citizen.
Comfortable using Zoom and other online communication tools.
No prior insurance experience is required — only a strong drive to succeed and a willingness to learn.

Advanced Micro Devices

San Jose, CA 95123

Broadcom

San Jose, CA 95112

MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design.
Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration.
Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint.
Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
Experience in synthesis, CDC, static timing analysis.
Exposure to SDF annotated simulations with good understanding of parasitic delays.
Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
Strong analytical thinking and problem-solving skills with excellent attention to details.
Must be organized, self-motivated and able to work effectively across internal and end customers teams.
Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.