2142 Electrical Design Engineer jobs in Union City,CA

Electric Standards and Strategy Engineer

PG&E Corporation

Oakland, CA 94612

BS Degree in Electrical OR Civil Engineering from an accredited curriculum in the US or the equivalent from outside the US
3 years of experience in electrical or civil engineering, planning and/or operations

Adecco

Santa Clara, CA 95051

7 years of experience
Background in electrical test and validation, either in a MFG test group, RMA product diagnostics/repair team, or supporting an ENG design team
Can operate oscilloscopes, DMMs, and other test equipment independently
Ability so solder/desolder/rework SMT PCBs of current technology sizes
General low voltage electrical knowledge 0-24V
General electo-mechanical assembly / disassembly understanding ESD mitigation
Can make electrical cables from sketches
Highly detail focused, need careful and disciplined execution of tasks with a lot of steps

Apple, Inc.

Cupertino, CA 95015

Samsung Electronics Co.

San Jose, CA 95112

10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
Demonstrated successful architectural through RTL design experience on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Knowledge of system caches and directory snoop filter protocols.
Familiarity with different on-chip network topologies: mesh, ring, crossbar.
Experience in leading and mentoring a team of engineers.
Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
Knowledge of memory subsystem design including coherent cache design.